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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9483 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 triple 8-bit, 140 msps a/d converter functional block diagram 8 t/h quantizer ad9483 timing r ain r ain g ain g ain b ain b ain encode encode ds ds vref out rvref in gvref in bvref in v cc v dd gnd pd i/p oms clkout clkout d b b 7-0 d b a 7-0 d g b 7-0 d g a 7-0 d r b 7-0 d r a 7-0 8 t/h quantizer 8 t/h quantizer control +2.5v features 140 msps guaranteed conversion rate 100 msps low cost version available 330 mhz analog bandwidth 1 v p-p analog input range internal +2.5 v reference differential or single-ended clock input 3.3 v/5.0 v three-state cmos outputs single or demultiplexed output ports data clock output provided low power: 1.0 w typical +5 v converter power supply applications rgb graphics processing high resolution video lcd monitors and projectors micromirror projectors plasma display panels scan converters general description the ad9483 is a triple 8-bit monolithic analog-to -digital converter optimized for digitizing rgb graphics signals from personal computers and workstations. its 140 msps encode rate capability and full-power analog bandwidth of 330 mhz supports display resolutions of up to 1280 1024 at 75 hz with sufficient input bandwidth to accurately acquire and digitize each pixel. to minimize system cost and power dissipation, the ad9483 includes an internal +2.5 v reference and track-and-hold cir- cuit. the user provides only a +5 v power supply and an en- code clock. no external reference or driver components are required for many applications. the digital outputs are three- state cmos outputs. separate output power supply pins sup- port interfacing with 3.3 v or 5 v logic. the ad9483s encode input interfaces directly to ttl, cmos, or positive-ecl logic and will operate with single-ended or differential inputs. the user may select dual channel or single channel digital outputs. the dual channel (demultiplexed) mode interleaves adc data through two 8-bit channels at one- half the clock rate. operation in dual channel mode reduces the speed and cost of external digital interfaces while allowing the adcs to be clocked to the full 140 msps conversion rate. in the single channel mode, all data is piped at the full clock rate to the channel a outputs and the adcs conversion rate is limited to 100 msps. a data clock output is provided at the channel a output data rate for both dual-channel or single- channel output modes. fabricated in an advanced bicmos process, the ad9483 is provided in a space-saving 100-lead mqfp surface mount plas- tic package (s-100) and is specified over the 0 c to +85 c temperature range.
C2C rev. a ad9483Cspecifications (v cc = +5 v, v dd = +3.3 v, external reference, encode = maximum conversion rate differential pecl) test AD9483KS-140 ad9483ks-100 parameter temperature level min typ max min typ max units resolution 8 8 bits dc accuracy differential nonlinearity +25 c i 0.8 1.25/C1.0 0.8 1.25/C1.0 lsb full vi 1.50/C1.0 1.50/C1.0 lsb integral nonlinearity +25 c i 0.9 1.50/C1.50 0.9 1.50/C1.50 lsb full vi 1.75/C1.75 1.75/C1.75 lsb no missing codes full vi guaranteed guaranteed gain error 1 +25 ci 1 2 1 2% fs gain tempco 1 full v 160 160 ppm/ c analog input input voltage range (with respect to ain ) full v 512 512 mv pCp compliance range ain or ain full v 1.8 3.2 1.8 3.2 v input offset voltage +25 ci 4 16 4 16 mv full vi 20 20 mv input resistance +25 c i 35 83 35 83 k w full vi 25 25 k w input capacitance +25 cv 4 4 pf input bias current +25 c i 17 36 17 36 m a full vi 50 50 m a analog bandwidth, full power +25 c v 330 330 mhz reference output output voltage full vi +2.4 +2.5 +2.6 +2.4 +2.5 +2.6 v temperature coefficient full v 110 110 ppm/ c switching performance maximum conversion rate full vi 140 100 msps minimum conversion rate full iv 10 10 msps encode pulsewidth high (t eh ) +25 c iv 2.8 50 4.0 50 ns encode pulsewidth low (t el ) +25 c iv 2.8 50 4.0 50 ns aperture delay (t a ) +25 c v 1.5 1.5 ns aperture delay matching +25 c v 100 100 ps aperture uncertainty (jitter) +25 c v 2.3 2.3 ps rms data sync setup time (t sds ) +25 civ0 0 ns data sync hold time (t hds ) +25 c iv 0.5 0.5 ns data sync pulsewidth (t pwds ) +25 c iv 2.0 2.0 ns output valid time (t v ) 2 full vi 4.0 6.3 4.0 6.3 ns output propagation delay (t pd ) 2 full vi 8.0 10 8.0 10 ns clock valid time (t cv ) 3 full vi 3.8 6.2 3.8 6.2 ns clock propagation delay (t cpd ) 3 full vi 8.0 10 8.0 10 ns data to clock skew (t v Ct cv ) full vi C1.0 0 1.0 C1.0 0 1.0 ns data to clock skew (t pd Ct cpd ) full vi C2.0 0 2.0 C2.0 0 2.0 ns digital inputs input capacitance +25 cv 3 3 pf differential inputs differential signal amplitude (v id ) full iv 400 400 mv high input voltage (v ihd ) full iv 0.4 v cc 0.4 v cc v low input voltage (v ild ) full iv 0 0 v common-mode input (v icm ) full iv 1.5 1.5 v high level current (i ih ) full vi 1.2 1.2 ma low level current (i il ) full vi 1.2 1.2 ma vref in input resistance +25 c v 2.5 2.5 k w
C3C rev. a ad9483 test AD9483KS-140 ad9483ks-100 parameter temperature level min typ max min typ max units single-ended inputs high input voltage (v ih ) full iv 2.0 v cc 2.0 v cc v low input voltage (v il ) full iv 0 0.8 0 0.8 v high level current (i ih ) full vi 1 1 ma low level current (i il ) full vi 1 1 ma digital outputs logic 1 voltage full vi v dd C 0.05 v dd C 0.05 v logic 0 voltage full vi 0.05 0.05 v output coding binary binary power supply v cc supply current full vi 215 215 ma v dd supply current full vi 60 60 ma total power dissipation 4 full vi 1.0 1.3 1.0 1.3 w power-down supply current +25 cv 420 420ma power-down dissipation +25 c v 20 100 20 100 mw dynamic performance 5 transient response +25 c v 1.5 1.5 ns overvoltage recovery time +25 c v 1.5 1.5 ns signal-to-noise ratio (snr) (without harmonics) f in = 19.7 mhz +25 c v 45 45 db f in = 49.7 mhz +25 c i 41 44 41 44 db f in = 69.7 mhz +25 c v 44 44 db signal-to-noise ratio (sinad) (with harmonics) f in = 19.7 mhz +25 c v 44 44 db f in = 49.7 mhz +25 c i 40 43 40 43 db f in = 69.7 mhz +25 c v 42 42 db effective number of bits f in = 19.7 mhz +25 c v 7.0 7.0 bits f in = 49.7 mhz +25 c i 6.4 6.8 6.4 6.8 bits f in = 69.7 mhz +25 c v 6.8 6.8 bits 2nd harmonic distortion f in = 19.7 mhz +25 c v 63 63 dbc f in = 49.7 mhz +25 c i 50 58 50 58 dbc f in = 69.7 mhz +25 c v 51 51 dbc 3rd harmonic distortion f in = 19.7 mhz +25 c v 56 56 dbc f in = 49.7 mhz +25 c i 46 54 46 54 dbc f in = 69.7 mhz +25 c v 51 51 dbc crosstalk full v 55 55 db notes 1 gain error and gain temperature coefficient are based on the adc only (with a fixed +2.5 v external reference). 2 t v and t pdf are measured from the threshold crossing of the encode input to valid ttl levels at the digital outputs. the output ac load du ring test is 5 pf. 3 t cv and t cpd are measured from the threshold crossing of the encode input to valid ttl levels at the digital outputs. the output ac load du ring test is 20 pf. 4 measured under the following conditions: analog input is C1 dbfs at 19.7 mhz. 5 snr/harmonics based on an analog input voltage of C1.0 dbfs referenced to a 1.024 v full-scale input range. typical thermal impedance for the s-100 (mqfp) 100-lead package: q jc = 10 c/w, q ca = 17 c/w, q ja = 27 c/w. specifications subject to change without notice.
ad9483 C4C rev. a caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9483 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings* v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 v v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 v analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . v cc to 0.0 v vref in, vref out . . . . . . . . . . . . . . . . . . . . v cc to 0.0 v digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . v cc to 0.0 v digital output current . . . . . . . . . . . . . . . . . . . . . . . . 20 ma operating temperature . . . . . . . . . . . . . . . . . . . 0 c to +85 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . . +175 c maximum case temperature . . . . . . . . . . . . . . . . . . . +150 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may effect device reliability. explanation of test levels test level i C 100% production tested. ii C 100% production tested at +25 c and sample tested at specified temperatures. iii C periodically sample tested. iv C parameter is guaranteed by design and characterization testing. v C parameter is a typical value only. vi C 100% production tested at +25 c; guaranteed by design and characterization testing. table i. output coding step ainC ain code binary 255 3 0.512 v 255 1111 1111 254 0.508 v 254 1111 1110 253 0.504 v 253 1111 1101 129 0.006 v 129 1000 0001 128 0.002 v 128 1000 0000 127 C0.002 v 127 0111 1111 126 C0.006 v 126 0111 1110 2 C0.504 v 2 0000 0010 1 C0.508 v 1 0000 0001 0 C0.512 v 0 0000 0000 ordering guide temperature package package model range description option ad9483ks-100 0 c to +85 c plastic thin quad flatpack s-100b AD9483KS-140 0 c to +85 c plastic thin quad flatpack s-100b ad9483/pcb +25 c evaluation board warning! esd sensitive device
ad9483 C5C rev. a pin function descriptions pin number name function 1, 6, 7, 10, 20, 30, 40, 50, 60, 70, 73, 77, 78, 80, 81, 95, 96, 100 gnd ground 2 encode encode clock for adc (adc samples on rising edge of encode). 3 encode encode clock complement (adc samples on falling edge of encode ). 4 ds data sync aligns output channels in dual-channel mode. 5 ds data sync complement. 8 dco data clock output. clock output at channel a data rate. 9 dco data clock output complement. 11, 21, 31, 41, 51, 61, 71 v dd output power supply. nominally 3.3 v. 79, 82, 83, 93, 94, 98, 99 v cc converter power supply. nominally 5.0 v. 12C19 d b b 7 Cd b b 0 digital outputs of converter b, channel b. d b b 7 is the msb. 22C29 d b a 7 Cd b a 0 digital outputs of converter b, channel a. d b a 7 is the msb. 32C39 d g b 7 Cd g b 0 digital outputs of converter g, channel b. d g b 7 is the msb. 42C49 d g a 7 Cd g a 0 digital outputs of converter g, channel a. d g a 7 is the msb. 52C59 d r b 7 Cd r b 0 digital outputs of converter r, channel b. d r b 7 is the msb. 62C69 d r a 7 Cd r a 0 digital outputs of converter r, channel a. d r a 7 is the msb. 72 nc no connect. 74 oms selects single channel or dual channel output mode, (high = single, low = dem uxed). 75 i/p selects interleaved or parallel output mode, (high = interleaved, low = parallel). 76 pd power-down and three-state select (high = power-down). 84 r ain analog input complement for converter r. 85 r ain analog input true for converter r. 86 r ref in reference input for converter r (+2.5 v typical, 10%). 87 g ain analog input complement for converter g. 88 g ain analog input true for converter g. 89 g ref in reference input for converter g (+2.5 v typical, 10%). 90 b ain analog input complement for converter b. 91 b ain analog input true for converter b. 92 b ref in reference input for converter b (+2.5 v typical, 10%). 97 ref out internal reference output (+2.5 v typical); bypass with 0.01 m f to ground.
ad9483 C6C rev. a pin configuration plastic thin quad flatpack (s-100b) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 5 4 3 2 7 6 9 8 1 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 26 25 28 27 30 29 32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 50 31 37 76 77 78 79 74 75 72 73 70 71 80 65 66 67 68 63 64 61 62 59 60 69 57 58 55 56 53 54 51 52 pin 1 identifier top view (pins down) ad9483 gnd v cc v cc ref out gnd gnd v cc v cc b ref in b ain b ain g ref in g ain g ain r ref in r ain r ain v cc v cc gnd v dd d g b 7 d g b 6 d g b 5 d g b 4 d g b 3 d g b 2 d g b 1 d g b 0 gnd v dd d g a 7 d g a 6 d g a 5 d g a 4 d g a 3 d g a 2 d g a 1 d g a 0 gnd gnd v cc gnd gnd pd i/p oms gnd nc v dd gnd d r a 0 d r a 1 d r a 2 d r a 3 d r a 4 d r a 5 d r a 6 d r a 7 v dd gnd d r b 0 d r b 1 d r b 2 d r b 3 d r b 4 d r b 5 d r b 6 d r b 7 v dd gnd encode encode ds ds gnd gnd dco dco gnd v dd d b b 7 d b b 6 d b b 5 d b b 4 d b b 3 d b b 2 d b b 1 d b b 0 gnd v dd d b a 7 d b a 6 d b a 5 d b a 4 d b a 3 d b a 2 d b a 1 d b a 0 gnd nc = no connect
ad9483 C7C rev. a timing ain encode encode d7Cd0 clock out clock out sample nC1 sample n sample n+3 sample n+4 sample n+2 sample n+1 t eh t el 1/f s t a data nC5 data nC4 data nC3 data nC2 data nC1 data n t cpd t pd t v t cv figure 1. timingsingle channel mode t cpd t a t eh t el 1/f s interleaved data out sample nC2 encode encode clkout clkout sample n+1 sample n sample n+3 sample n+4 sample nC1 data nC3 data nC2 data nC1 data n t pd t v data nC2 port b d7Cd0 port a d7Cd0 port b d7Cd0 port a d7Cd0 ds ds ain t hds t sds sample n+5 sample n+6 invalid if out of sync data nC4 if in sync invalid if out of sync data nC5 if in sync invalid if out of sync data nC4 if in sync invalid if out of sync data nC5 if in sync data nC7 or nC6 data nC7 or nC8 data nC6 or nC7 data nC8 or nC7 data nC8 or nC7 data nC6 or nC7 data nC9 or nC8 data nC7 or nC8 data nC7 or nC6 data nC3 data nC1 data n+1 data n data n+1 sample n+2 parallel data out t cv figure 2. timingdual channel mode
ad9483 C8C rev. a equivalent circuits v cc ain ain ad9483 figure 3. equivalent analog input circuit v cc vref in ad9483 500 v 2k v figure 4. equivalent reference input circuit v cc encode ds ad9483 encode ds 7.5k v 300 v 17.5k v 300 v figure 5. equivalent encode and data select input circuit v cc ad9483 demux figure 6. equivalent demux input circuit v dd digital outputs ad9483 figure 7. equivalent digital output circuit v cc ad9483 vref out figure 8. equivalent reference output circuit v cc ad9483 digital inputs figure 9. equivalent digital input circuit
ad9483 C9C rev. a typical performance characteristicsC f in C mhz 050 0 db C0.5 C1 C1.5 C2 C2.5 C3 C3.5 C4 C4.5 150 250 300 400 450 C5 100 200 350 nyquist frequency (70mhz) C3db (333mhz) figure 10. frequency response: f s = 140 msps f in C mhz 05 C70 db C60 C50 C40 C30 C20 C10 0 10 50 100 200 250 2.5 7.5 25 75 150 figure 11. crosstalk vs. f in : f s = 140 msps temperature C 8 c 0 db 100 C50 C55 C60 C65 C70 C75 C80 10 20 30 40 50 60 70 80 90 figure 12. crosstalk vs. temperature: f in = 70 mhz temperature C 8 c C40 0 2.5 C20 20 40 60 80 100 2.48 2.46 2.44 2.42 2.4 volts figure 13. reference voltage vs. temperature v cc C v 3 2.6 2.5 2.4 2.3 2.2 3.2 3.4 3.6 3.8 4 4.2 v ref 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 6.2 6.4 2.1 2 figure 14. reference voltage vs. power supply voltage 14 12 13 0 2.6 2.5 2.4 12345678910 volts 2.3 2.2 2.1 2 1.9 1.8 1.7 1.6 11 15 i ref C ma figure 15. reference voltage vs. reference load
ad9483 C10C rev. a Ctypical performance characteristics load capacitance C pf 9 5101520 ns 8.5 8 7.5 7 6.5 6 5.5 5 25 30 4.5 4 t pd 3.3v t v 3.3v t v 5v t pd 5v figure 16. clock output delay vs. capacitance t pd t v v dd C v 8 3 3.3 ns 7 6 5 4 3 2 1 0 3.6 3.9 4.2 4.5 4.75 5 5.25 5.5 9 figure 17. output delay vs. v dd t pd 3.3v t pd 5v t v 3.3v t v 5v temperature C 8 c 7.5 ns C40 0 50 100 7 6.5 6 5.5 5 4.5 4 8 8.5 9 figure 18. output delay vs temperature 4 i oh C ma volts 0 2 10 16 20 5 3 1 0.5 0 v dd = +3.3v 1.5 2 2.5 3.5 4.5 468 1214 18 v dd = +5v figure 19. output voltage high vs. output current v dd = +3.3v v dd = +5v i ol volts 0 5 10 15 20 2 1.6 1.2 0.8 0.2 0 0.4 0.6 1 1.4 1.8 figure 20. output voltage low vs. output current v dd C v mw 600 0 500 400 300 200 100 3 3.5 4 4.5 5 5.5 figure 21. output power vs. v dd , c load = 10 pf
ad9483 C11C rev. a f s C msps 0 db 30 30 60 140 180 34 38 42 46 50 100 snr sinad 32 36 40 44 48 figure 22. snr vs. f s : f in = 19.7 mhz 3rd harmonic 2nd harmonic f s C msps 0 db 25 50 130 170 C75 90 C70 C65 C60 C55 C50 figure 23. harmonic distortion vs. f s : f in = 19.7 mhz mhz 0 db C90 10 20 30 40 50 60 70 80 90 100 C80 C70 C60 C50 C40 C30 C20 C10 0 fundamental = C0.5dbfs snr = 45.8db sinad = 45.2db 2nd harmonic = 69.8db 3rd harmonic = 61.6db figure 24. spectrum: f s = 140 msps, f in = 19.57 mhz snr sinad f s C msps 0 db 30 20 140 180 34 38 42 46 50 32 36 40 44 48 40 60 80 100 120 160 200 figure 25. snr vs f s : f in = 71.7 mhz 3rd harmonic 2nd harmonic f s C msps 0 db C36 40 80 155 175 120 C38 C40 C42 C44 C46 C48 C50 C52 C54 C56 figure 26. harmonic distortion vs f s : f in = 71.7 mhz mhz 0 db C90 10 20 30 40 50 60 70 80 90 100 C80 C70 C60 C50 C40 C30 C20 C10 0 fundamental = C0.5dbfs snr = 44.6db sinad = 37.6db 2nd harmonic = 63.1db 3rd harmonic = 39.1db figure 27. spectrum: f s = 140 msps, f in = 70.3 mhz
ad9483 C12C rev. a snr sinad f s = 140 msps f in = 19.3mhz 25% 1.8 db 30 28% 2 31% 2.2 38% 2.7 45% 3.2 52% 3.7 59% 4.2 66% 4.7 32 34 36 38 40 42 44 46 encode duty cycle C % encode pulsewidth C ns 73% 5.2 76% 5.4 figure 28. snr vs. clock pulsewidth (t pwh ): f s = 140 msps f in C mhz 050 55 db 100 150 200 250 50 45 40 35 30 nyquist frequency (70.0mhz) sinad snr figure 29. snr vs. f in : f s = 140 msps temperature C 8 c C25 C60 db C56 C52 C48 C44 C40 0 40 60 80 100 figure 30. 3rd harmonic vs. temperature, f s = 140 msps sinad snr temperature C 8 c C25 db 44 43 42 41 40 0 406080100 45 46 figure 31. snr vs. temperature, f s = 140 msps temperature C 8 c C25 C60 db C55 C50 C45 C40 0 40 60 80 100 C65 C70 figure 32. 2nd harmonic vs. temperature, f s = 140 msps mhz 0 db C90 10 20 30 40 50 60 70 80 90 100 C80 C70 C60 C50 C40 C30 C20 C10 0 f1 = 55.0mhz f2 = 56.0mhz f1 = f2 = C7.0dbfs C100 figure 33. two tone intermodulation distortion
ad9483 C13C rev. a application notes theory of operation the ad9483 combines analog devices patented magamp bit- per-stage architecture with flash converter technology to create a high performance, low power adc. for ease of use the part includes an on board reference and input logic that accepts ttl, cmos or pecl levels. each of the three analog input signals is buffered by a high speed differential amplifier and applied to a track-and-hold (t/h) circuit. this t/h captures the value of the input at the sampling instant and maintains it for the duration of the conversion. the sampling and conversion process is initiated by a rising edge on the encode input. once the signal is captured by the t/h, the four most significant bits (msbs) are sequentially encoded by the magamp string. the residue signal is then encoded by a flash comparator string to generate the four least significant bits (lsbs). the comparator outputs are decoded and com- bined into the 8-bit result. if the user has selected single channel mode (oms = high) the 8-bit data word is directed to an a output bank. data are strobed to the output on the rising edge of the encode input with four pipeline delays. if the user has selected dual channel mode (oms = low) the data are alternately directed between the a and b output banks and the data has five pipeline delays. at power-up, the n sample data can appear at either the a or b port. to align the data in a known state, the user must strobe data sync (ds, ds ) per the conditions described in the timing section. graphics applications the high bandwidth and low power of the ad9483 makes it very attractive for applications that require the digitization of presampled waveforms, wherein the input signal rapidly slews from one level to another, then is relatively stable for a period of time. examples of these include digitizing the output of com- puter graphic display systems, and very high speed solid state imagers. these applications require the converter to process inputs with frequency components well in excess of the sampling rate (often with subnanosecond rise times), after which the a/d must settle and sample the input in well under one pixel time. the architec- ture of the ad9483 is vastly superior to older flash architec- tures, which not only exhibit excessive input capacitance (which is very hard to drive), but can make major errors when fed a very rapidly slewing signal. the ad9483s extremely wide bandwidth track/hold circuit processes these signals without difficulty. using the ad9483 good high speed design practices must be followed when using the ad9483. decoupling capacitors should be physically as close as possible to the chip to obtain maximum benefit. we recommend placing a 0.1 m f capacitor at each power ground pin pair (14 total) for high frequency decoupling and including one 10 m f capacitor for local low frequency decoupling. each of the three vref in pins should also be decoupled by a 0.1 m f capacitor. the part should be located on a solid ground plane and output trace lengths should be short (<1 inch) to minimize transmis- sion line effects. this will avoid the need for termination resis- tors on the output bus and reduces the load capacitance that needs to be driven, which in turn minimizes on-chip noise due to heavy current flow in the outputs. we have obtained opti- mum performance on our evaluation board by tying all v cc pins to a quiet analog power supply system and tying all gnd pins to a quiet analog system ground. minimum encode rate the minimum sampling rate for the ad9483 is 10 mhz for the 140 msps and 100 msps versions. to achieve this sampling rate, the track/hold circuit employs a very small hold capacitor. when operated below the minimum guaranteed sampling rate, the t/h droop becomes excessive. this is first observed as an increase in offset voltage, followed by degraded linearity at even lower frequencies. lower effective sampling rates may be easily supported by oper- ating the converter in dual port output mode and using only one output channel. a majority of the power dissipated by the ad9483 is static (not related to conversion rate), so the penalty for clocking at twice the desired rate is not high. digital inputs snr performance is directly related to the sampling clock sta- bility in a/d converters, particularly for high input frequencies and wide bandwidths. encode and data select (ds) can be driven differentially or single-ended. for single-ended operation, the complement inputs ( encode , ds ) are internally biased to v dd /3 (~1.5 v) by a high impedance on-chip resistor divider (figure 5), but they may be externally driven to establish an alternate threshold if desired. a 0.1 m f decoupling capacitor to ground is sufficient to maintain a threshold appropriate for ttl or cmos logic. when driven differentially, encode and ds will accommo- date differential signals centered between 1.5 v and 4.5 v with a total differential swing 3 800 mv (v id 3 400 mv). note the 6-diode clock input protection circuitry in figure 5. this limits the differential input voltage to 2.1 v. when the diodes turn on, current is limited by the 300 w series resistor. exceeding 2.1 v across the differential inputs will have no im- pact on the performance of the converter, but be aware of the clock signal distortion that may be produced by the nonlinear impedance at the converter. v id v id v ih d v ic m v il d v in d v ic m v il d enc enc clock clock enc enc clock 0.1 m f driving differential inputs differentially driving differential inputs single-endedly figure 34. input signal level definitions
ad9483 C14C rev. a adc gain control each of the three adc channels has independent limited gain control. the full-scale signal amplitude for a given adc is set by the dc voltage on its vref in pin. the equation relating the full scale amplitude to vref in is as follows: fs = (0.4) (vref in). the three adcs are optimized for a full-scale signal ampli- tude of 1 v, but will accommodate up to 10% variation. adc offset control the offset for each of the three adcs can be independently controlled. for a single-ended analog input where the analog input is connected to a reference, offset can be adjusted simply by adjusting the dc voltage of the reference. for differential analog inputs, the user must provide the offset in their signal. offset can be adjusted up or down as far as the common-mode input range will allow. power dissipation power dissipation for the ad9483 has two components, v cc and v dd . power dissipation from v cc is relatively constant for a given supply voltage, whereas power dissipation from v dd can vary greatly. v cc supplies power to the analog circuity. v dd supplies power to the digital outputs and can be approximated by the following equation: p ( v dd ) = 1/2 c v 2 f n c = output load capacitance v =v dd supply voltage f = encode frequency n = number of outputs switching nominally, c = 10 pf, v = 3.3 v, f = 140 msps, and n = 26. n comes from the 24 output bits plus two clock outputs, p(v dd ) = 197 mw. power-down the power-down function allows users to reduce power dissipa- tion when output data is not required. a ttl/cmos high signal on pin 76, (pd), shuts down most of the chip and brings the total power dissipation to less than 100 mw. the internal bandgap voltage reference remains active during power-down mode to minimize reactivation time. if the power-down function is not desired, the pd pin should be tied to ground or held to a ttl/cmos low level. bandgap voltage reference the ad9483 internal reference, vref out (pin 97), provides a simple, cost effective reference for many applications. it exhib- its reasonable accuracy and excellent stability over power supply and temperature variations. the reference output can be used to set the three adcs gain and offset. the reference is capable of providing up to 1 ma of additional current beyond the require- ments of the ad9483. as the adc gain and offset are set by the reference inputs, some applications may require a reference with greater accuracy or temperature performance. in these cases, an external refer- ence may be connected directly to the vref in pins. vref out, if unused, should be left floating. note, each of the three vref in pins will require up to 1 ma of current. modes of operation the ad9483 has three modes of operation, single channel output mode, and a dual channel output mode with two pos- sible data formats, interleaved or parallel. two pins control w hich mode of operation the chip is in, pin 74 output mode select (oms) and pin 75 in terleaved/parallel select (i/p). table ii shows the configuration required for each mode. table ii. output mode selection mode oms i/p dual channelparallel low low dual channelinterleaved low high single channel high dont care demuxed output mode in demuxed mode, (pin 74 oms = low), the adc output data are alternated between the two output ports (port a and port b). this limits the data output rate to 1/2 the rate of encode, and facilitates conversion rates up to 140 msps. demuxed output m ode is recommended for guaranteed opera- tion above 100 msps, but may be enabled at any specified conversion rate. two data formats are possible in dual channel output mode, parallel data out and interleaved data out. pin 75 i/p should be low for parallel format and high for interleaved format. figures 1 and 2 show the timing requirements for each format. note that the data sync input, (ds), is required in dual chan- nel output mode for both formats. the section on data sync describes the requirements of the data sync input. as shown in figures 1 and 2, when using the interleaved data format, a sample is taken on an encode rising edge n. the resulting data is produced on an output port following the fifth rising edge of encode after the sample was taken, (five pipe- line delays). the following sample, (n+1), will be produced on the opposite port, also five pipeline delays after it was taken. the state of clkout when the sample was taken will deter- mine out of which port the data will come. if clkout was low, the data will come out port a. if clkout was high, the data will come out port b. in order to achieve parallel data format on the two output data ports, the data is internally aligned. this is accomplished by adding an extra pipeline delay to just the a data port. thus, data coming out port a will have six pipeline delays and data coming out port b will have five pipeline delays. as with the interleaved format, the state of data sync when a sample is taken will determine out of which port the data will come. if clkout was low, the data will come out port a. if clk- out was high, the data will come out port b.
ad9483 C15C rev. a data sync the data sync input, ds, is required to be driven for most applications to guarantee at which output port a given sample will appear. when ds is held high, the adc data outputs and clock outputs do not switchthey are held static . synchronization is accomplished by the assertion (falling edge) of ds, within the timing constraints t sds and t hds relative to an encode rising edge. (on initial synchronization t hds is not relevant.) if ds falls t sds before a given encode rising edge n, the analog value at that point in time will be digitized and available at port a five cycles later (interleaved mode). the very next sample, n+l, will be sampled by the next rising encode edge and available at port b five cycles after that encode edge (interleaved mode). in dual parallel mode the a port has a six cycle latency, the b port has a five cycle latency as described in demuxed outputs mode section. ds can be asserted once per video line if desired by using the horizontal sync signal (hsync). the start of hsync should occur after the end of active video by at least the chip latency. the hsync front porch is usually much greater than this in a typical sxga system. if this is true in a given system then ds can be reset high by the hsync leading edge (the samples at that point should not be required in a typical system). ds can then be reasserted (brought low), by triggering from hsync trailing edgeobserving t sds of the next rising encode edge. the first pixel data (on a port) would be available five cycles after the first rising encode after hsync goes high. it is possible to use the phase of the data clock outputs and software programming to accommodate situations where ds is not driven. the data clock outputs (clkout and clkout ) can be used to determine when data is valid on the output ports. in these cases ds should be grounded and ds left floating or connected to v cc . if clkout was low when a given sample was taken, the digitized value will be available on port a, five cycles later. data sync has no effect when single channel mode is selected, it should be grounded figure 2 shows how to use ds properly. the ds rising edge does not have any special timing requirements except that no data will come out of either port while it is held high. the falling edge of ds must, however, meet a minimum setup-and- hold time with respect to the rising edge of encode. single channel outputs mode in single channel mode, (pin 74 oms = high), the timing of the ad9483 is similar to any high speed adc (figure 1). a sample is taken on every rising edge of encode, and the re- sulting data is produced on the output pins following the fourth rising edge of encode after the sample was taken, (four pipe- line delays). the output data are valid t pd after the rising edge of encode, and remain valid until at least t v after the next rising edge of encode. the maximum conversion rate in the mode should be limited to 100 msps. this is recommended because the guaranteed out- put data valid time minus the propagation delay is only 4 ns at 100 msps. this is about as fast as standard logic is able to capture the data with reasonable design margins. the ad9483 will operate faster in this mode if the user is able to capture the data. when operating in single channel mode, all data comes out the a ports while the b ports are held static in a random state. data clock outputs the data clock outputs will switch at two potential frequencies. in single channel mode, where all data comes out of port a at the full encode rate, the data clock outputs switch at the same frequency as the encode. in dual channel mode, where the data alternates between the two ports, each of which operate at 1/2 the full encode rate, the data clock outputs also switch at 1/2 the full encode rate. the data clock outputs have two potential purposes. the first is to act as a latch signal for capturing output data. in order to do this, simply drive the data latches with the appropriate data clock output. the second use is in dual channel data mode to help determine out of which data port data will come out. refer to figure 2 for a complete timing diagram, but in this mode, a rising edge on data clock will correspond to data switching on data port b. layout and bypassing considerations proper high speed layout and bypassing techniques should be used with the ad9483. each v cc and v dd power pin should be bypassed as close to the pin as possible with a 0.01 m f to 0.1 m f capacitor also, one 10 m f capacitor to ground should be used per supply per board. the vref out pin and each of the three vref in pins should also be bypassed with a 0.01 m f to 0.1 m f capacitor to ground. a single, substantial, low impedance ground plane should be place under and around the ad9483. try to maximize the distance between the sensitive analog signals, (ain, vref), and the digital signals. capacitive loading on the digital outputs should be kept to a minimum. this can be facilitated by keeping the traces short and in the case of the clock outputs by driving as few other devices as possible. socketing the ad9483 should also be avoided. try to match trace lengths of similar signals to avoid mismatches in propagation delays, (the encode inputs, analog inputs, digital outputs). power supplies at power up, v cc must come up before v dd . v cc is considered the converter supply, nominally 5.0 v ( 5.0%) v dd is consider output power supply, nominally 3.3 v ( 10%) or 5.0 v ( 5%). at power off, v dd must turn off first. failure to observe the correct power supply sequencing many damage this device.
ad9483 C16C rev. a evaluation board the ad9483 evaluation board offers an easy way to test the ad9483. it provides ac or dc biasing for the analog input, it generates the output latch clocks for single mode, dual parallel mode and dual interleaved mode. each of the three channels has a reconstruction dac (a port only). the board has several different modes of operation, and is shipped in the following configuration: single-ended ac coupled analog input (1 v p-p centered at ground) differential clock inputs (pecl) (see encode section for ttl drive) internal voltage references connected to externally buff- ered on-chip reference (vref out) preset for dual mode interleaved analog input the evaluation board accepts a 1 v p-p input signal centered at ground for ac coupled input mode (set jumpers w4, w5, w12, w13, w18, w17 to jump pin 1 to pin 2). this signal biased up to 2.5 v by the on-chip reference. note: input signal should be bandlimited (filtered) prior to sampling to avoid aliasing. the analog inputs are terminated to ground by a 75 w resistor on the board. the analog inputs are ac coupled through 0.1 m f caps c2, c4, c6 on top of the board. these can be increased to accommodate lower fre- quency inputs if desired using test points pr1Cpr6 on bot- tom of board. in dc coupled input mode (set jumpers w4, w5, w12, w13, w18, w17 to jump pin 3 to pin 2 ) the board accepts typical video level signal levels (0 mv to 700 mv) the signal is level shifted and amplified to 1 v p-p by the ad8055 preamp. trimpots r98Cr100 are used to adjust dc black level to 2 v at adc inputs. encode the ad9483 encode input can be driven two ways. 1. differential pecl (v lo = 3, v hi = 4 nominal). it is shipped in this mode. 2. single ended ttl or cmos. (at encode barCremove 50 w termination resistor r10, add 0.1 m f capacitor c7) table iii. evaluation board jumper settings mode w7 (oms) w6 (i/p) w11 (a_lat) w11 (b_lat) dual channel/parallel low low data_clk_out (4C5) data_clk_out (2C3) dual channel/interleaved low high data_clk_out (5C6) data_clk_out (2C3) single high dont care data_clk_out (5C6) nc design notes maximum frequency for parallel is 140 mhz. maximum frequency for interleaved is 140 mhz. maximum frequency for single is 100 mhz. ds is tied to ground through a 50 w resistor. ds is left floating. voltage reference the ad9483 has an internal 2.5 v voltage reference (vref out). this is buffered externally on board to support addi- tional level shifting circuitry (the ad9483 vref out pin can drive the three vref in pins in applications where level shifting is not required with no additional buffering). an external refer- ence may be employed instead to drive each vref in pin inde- pendently (requires moving jumpers w14, w15 and w16). single channel mode single channel mode sets the ad9483 to produce data on every clock cycle on output port a only. the maximum speed in single channel mode is 100 msps. dual channel modes (outputs clocked at 1/2 encode clock) dual channel interleaved sets the adc to produce data alternately on port a and port b. the maximum speed in this mode is 140 msps. dual channel parallel sets the adc to produce data concurrently on port a and port b. maximum speed in this mode is 140 msps. dac out the dac output is a representation of the data on output port a only. the dac is terminated on the board into 75 w . full- scale voltage swing at dac output is nominally 0 mv to 800 mv when terminated into external 75 w (doubly terminated). output port b is not reconstructed. the dac outputs are not filtered and will exhibit sampling noise. the dacs can be pow- ered down at w1, w2, and w3 (jumper not installed). data ready an output clock for latching the adc outputs is available at pin 1 at the 25-pin connector. its complement is located at pin 14. the clocks are terminated on the board by a 75 w thevenin termination to v d /2. the timing on these clock out- puts can be inverted at w9, w10 (jumper not installed). schematics the schematics for the evaluation board follow. (note bypass capacitors for adc are shown in figure 39.)
ad9483 C17C rev. a 84 85 87 88 90 91 86 89 92 97 ain a ain a ain b ain b ain c ain c a ref in ref out b ref in c ref in ref out c ref b ref a ref c ref b ref a ref 76 75 69 outa a0 68 outa a1 67 outa a2 66 outa a3 65 outa a4 64 outa a5 63 outa a6 62 outa a7 59 outa b0 58 outa b1 57 outa b2 56 outa b3 55 outa b4 54 outa b5 53 outa b6 52 outa b7 outa_a[0-7] outa_b[0-7] outa b0 outa b1 outa b2 outa b3 outa b4 outa b5 outa b6 outa b7 outa a0 outa a1 outa a2 outa a3 outa a4 outa a5 outa a6 outa a7 42 outb a7 43 outb a6 44 outb a5 45 outb a4 46 outb a3 47 outb a2 48 outb a1 49 outb a0 outb a7 outb a6 outb a5 outb a4 outb a3 outb a2 outb a1 outb a0 32 outb a7 33 outb a6 34 outb a5 35 outb a4 36 outb a3 37 outb a2 38 outb a1 39 outb a0 outb_b7 outb_b6 outb_b5 outb_b4 outb_b3 outb_b2 outb_b1 outb_b0 22 outc a7 23 outc a6 24 outc a5 25 outc a4 26 outc a3 27 outc a2 28 outc a1 29 outc a0 outc_a7 outc a6 outc a5 outc a4 outc a3 outc a2 outc a1 outc a0 12 outc b7 13 outc b6 14 outc b5 15 outc b4 16 outc b3 17 outc b2 18 outc b1 19 outc b0 outc b7 outc b6 outc b5 outc b4 outc b3 outc b2 outc b1 outc b0 outc_a[0-7] outc_b[0-7] outb a[0-7] outb b[0-7] data clk out ds encode 9 8 5 4 3 2 data clk out ds encode data clk out ds data_clk_out ds 74 oms i/p pwr dn enc enc r9 50 v j1 j2 encode encode r10 50 v smb c7 0.1 m f not installed smb vdd 1 3 2 1 3 2 w7 r101 100 v r102 100 v w6 ad9483 ad8055 bnc pr6 pr5 c6 0.1 m f j5 tp3 w18 r3 75 v 1 2 3 r91 274 v trim c r90 360 v 2 3 1 3 2 r105 200 v r6 1k v w17 6 u16 4 7 Cva va c ref c5 0.1 m f ad8055 bnc pr3 pr4 c4 0.1 m f j6 tp1 w12 r2 75 v 1 2 3 r88 274 v trim b r89 360 v 2 3 1 3 2 r104 200 v r5 1k v w13 6 u15 4 7 Cva va b ref c3 0.1 m f ad8055 bnc pr1 pr2 c2 0.1 m f j7 tp2 w4 r1 75 v 1 2 3 r87 274 v trim a r86 360 v 2 3 1 3 2 r103 200 v r4 1k v w5 6 u14 4 7 Cva va a ref c1 0.1 m f figure 35. adc and preamp section
ad9483 C18C rev. a outa a0 2 19 red a0 outa a1 3 18 red a1 outa a2 4 17 red a2 outa a3 5 16 red a3 outa a4 6 15 red a4 outa a5 7 14 red a5 outa a6 8 13 red a6 outa a7 9 12 red a7 gnd: 10 vd: 20 en c1 74lcx574 1 11 1d u6 gnd a_lat outa a [0-7] outa b0 2 19 red b0 outa b1 3 18 red b1 outa b2 4 17 red b2 outa b3 5 16 red b3 outa b4 6 15 red b4 outa b5 7 14 red b5 outa b6 8 13 red b6 outa b7 9 12 red b7 gnd: 10 vd: 20 en c1 74lcx574 1 11 1d u9 gnd b_lat outa b [0-7] outb a0 2 19 green a0 outb a1 3 18 green a1 outb a2 4 17 green a2 outb a3 5 16 green a3 outb a4 6 15 green a4 outb a5 7 14 green a5 outb a6 8 13 green a6 outb a7 9 12 green a7 gnd: 10 vd: 20 en c1 74lcx574 1 11 1d u10 gnd outb b0 2 19 green b0 outb b1 3 18 green b1 outb b2 4 17 green b2 outb b3 5 16 green b3 outb b4 6 15 green b4 outb b5 7 14 green b5 outb b6 8 13 green b6 outb b7 9 12 green b7 gnd: 10 vd: 20 en c1 74lcx574 1 11 1d u7 gnd outc a0 2 19 blue a0 outc a1 3 18 blue a1 outc a2 4 17 blue a2 outc a3 5 16 blue a3 outc a4 6 15 blue a4 outc a5 7 14 blue a5 outc a6 8 13 blue a6 outc a7 9 12 blue a7 gnd: 10 vd: 20 en c1 74lcx574 1 11 1d u8 gnd outc b0 2 19 blue b0 outc b1 3 18 blue b1 outc b2 4 17 blue b2 outc b3 5 16 blue b3 outc b4 6 15 blue b4 outc b5 7 14 blue b5 outc b6 8 13 blue b6 outc b7 9 12 blue b7 gnd: 10 vd: 20 en c1 74lcx574 1 11 1d u11 gnd vd r7 301 v r8 301 v vd r76 301 v r77 301 v outb a [0-7] outc a [0-7] outb b [0-7] outc b [0-7] figure 36. output latches section
ad9483 C19C rev. a comp d a db0 comp 1 2 23 19 24 27 ad9760 sleep a lat u1 74lcx86 r78 0 v dr vd r21 2k v vd : 14 gnd : 7 1 2 w9 vd c10 0.1 m f db1 db2 db3 db4 db5 db6 db7 db8 db9 clk i out a i out b fsadj ref lo io gnd: 20,26 1 2 3 4 5 6 7 8 9 10 red a0 red a1 red a2 red a3 red a4 red a5 red a6 red a7 28 15 16 17 18 c11 0.1 m f u2 21 r24 75 v r12 1k v c9 0.1 m f r19 1k v dac clk vd w1 vd vd vd dac clk dr dr r85 150 v r64 150 v r61 150 v r80 150 v r62 150 v r83 150 v clock line terminations comp d a db0 comp 1 2 23 19 24 27 ad9760 sleep b lat u1 74lcx86 r79 0 v dr vd r22 2k v vd : 14 gnd : 7 4 5 w10 vd c12 0.1 m f db1 db2 db3 db4 db5 db6 db7 db8 db9 clk i out a i out b fsadj ref lo io gnd: 20,26 1 2 3 4 5 6 7 8 9 10 green a0 green a1 green a2 green a3 green a4 green a5 green a6 green a7 28 15 16 17 18 c14 0.1 m f u4 21 r17 75 v r23 1k v c13 0.1 m f r11 1k v dac clk vd w3 comp d a db0 comp 1 2 23 19 24 27 ad9760 sleep a lat u1 74lcx86 dac_clk vd r73 2k v vd : 14 gnd : 7 9 10 w8 vd c15 0.1 m f db1 db2 db3 db4 db5 db6 db7 db8 db9 clk i out a i out b fsadj ref lo io gnd: 20,26 1 2 3 4 5 6 7 8 9 10 blue a0 blue a1 blue a2 blue a3 blue a4 blue a5 blue a6 blue a7 28 15 16 17 18 c17 0.1 m f u3 22 21 smb j10 r16 75 v r15 75 v r13 1k v c16 0.1 m f r20 1k v dac clk vd w2 22 smb j5 r18 75 v 22 smb j10 r14 75 v 8 6 3 figure 37. dacs and clock buffer section
ad9483 C20C rev. a c8 0.1 m f not installed smb u1 74lcx86 vd: 14 gnd: 7 11 12 13 ds r26 100 v red_a0 r_a0 r25 100 v red_a1 r_a1 r27 100 v red_a2 r_a2 r28 100 v red_a3 r_a3 r29 100 v red_a4 r_a4 r30 100 v red_a5 r_a5 r31 100 v red_a6 r_a6 r32 100 v red_a7 r_a7 r68 100 v red_b0 r_b0 r69 100 v red_b1 r_b1 r67 100 v red_b2 r_b2 r66 100 v red_b3 r_b3 r65 100 v red_b4 r_b4 r70 100 v red_b5 r_b5 r71 100 v red_b6 r_b6 r72 100 v red_b7 r_b7 r45 100 v green_a0 gr_a0 r44 100 v green_a1 gr_a1 r46 100 v green_a2 gr_a2 r47 100 v green_a3 gr_a3 r48 100 v green_a4 gr_a4 r43 100 v green_a5 gr_a5 r42 100 v green_a6 gr_a6 r41 100 v green_a7 gr_a7 r52 100 v green_b0 gr_b0 r53 100 v green_b1 gr_b1 r51 100 v green_b2 gr_b2 r50 100 v green_b3 gr_b3 r49 100 v green_b4 gr_b4 r54 100 v green_b5 gr_b5 r55 100 v green_b6 gr_b6 r56 100 v green_b7 gr_b7 r36 100 v blue_a0 bl_a0 r37 100 v blue_a1 bl_a1 r35 100 v blue_a2 bl_a2 r34 100 v blue_a3 bl_a3 r33 100 v blue_a4 bl_a4 r38 100 v blue_a5 bl_a5 r39 100 v blue_a6 bl_a6 r40 100 v blue_a7 bl_a7 r61 100 v blue_b0 bl_b0 r60 100 v blue_b1 bl_b1 r62 100 v blue_b2 bl_b2 r63 100 v blue_b3 bl_b3 r64 100 v blue_b4 bl_b4 r59 100 v blue_b5 bl_b5 r58 100 v blue_b6 bl_b6 r57 100 v blue_b7 bl_b7 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p20 p19 p18 p17 p16 p15 p14 p13 p12 p11 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 1 2 3 4 5 6 7 8 9 10 st4 u13 st1 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p20 p19 p18 p17 p16 p15 p14 p13 p12 p11 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 1 2 3 4 5 6 7 8 9 10 st4 u13 st1 p1 p2 p3 p4 p5 1 2 3 4 5 st8 p1 p2 p3 p4 p5 1 2 3 4 5 st7 gnd p1 p2 p3 p4 p5 1 2 3 4 5 st5 p1 p2 p3 p4 p5 1 2 3 4 5 st6 vd customer workspace 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 dr gnd r_a0 r_a1 r_a2 r_a3 r_a4 r_a5 r_a6 r_a7 gnd dr gnd r_b0 r_b1 r_b2 r_b3 r_b4 r_b5 r_b6 r_b7 gnd con-db25hf p1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 dr gnd gr_a0 gr_a1 gr_a2 gr_a3 gr_a4 gr_a5 gr_a6 gr_a7 gnd dr gnd gr_b0 gr_b1 gr_b2 gr_b3 gr_b4 gr_b5 gr_b6 gr_b7 gnd con-db25hf p2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 dr gnd bl_a0 bl_a1 bl_a2 bl_a3 bl_a4 bl_a5 bl_a6 bl_a7 gnd dr gnd bl_b0 bl_b1 bl_b2 bl_b3 bl_b4 bl_b5 bl_b6 bl_b7 gnd con-db25hf p3 gnd1 gnd2 gnd3 gnd4 gnd5 gnd6 gnd7 gnd8 gnd9 gnd10 test point grounds r74 50 v r75 50 v ds smb extra gates j3 j4 figure 38. digital outputs connectors and terminations section
ad9483 C21C rev. a ad9483 va Cva c18 10 m f c49 0.1 m f c41 0.1 m f ref out 2 3 4 7 6 2 3 1 c46 0.1 m f w14 c51 10 m f ext ref a 2 3 1 c47 0.1 m f w15 c53 10 m f ext ref b 2 3 1 c48 0.1 m f w16 c54 10 m f ext ref c r99 500 v r95 1.3k v r94 1.5k v trim c r96 1.3k v r97 1.5k v trim b r92 1.3k v r93 1.5k v trim a ref source select c ref b ref a ref r100 500 v r98 500 v 1 2 3 4 5 6 7 8 Cva ad9483 support logic C supply va ad9483 analog supply Cva ad9483 digital supply Cva ad9483 support logic + supply ext ref a ext ref b ext ref c ad9483 external references gnd tb1 c35 0.1 m f c36 0.1 m f c37 0.1 m f c38 0.1 m f c39 0.1 m f c40 0.1 m f c42 0.1 m f c43 0.1 m f c44 0.1 m f c45 0.1 m f c56 10 m f c52 10 m f c27 0.1 m f c28 0.1 m f c29 0.1 m f c30 0.1 m f c31 0.1 m f c32 0.1 m f c33 0.1 m f c34 0.1 m f c63 10 m f c60 0.1 m f c61 0.1 m f c62 0.1 m f c65 0.1 m f c20 0.1 m f c50 0.1 m f c19 0.1 m f c57 0.1 m f c23 0.1 m f c21 0.1 m f c22 0.1 m f c24 0.1 m f c25 0.1 m f c26 0.1 m f c55 10 m f va Cva vd vd bypass caps 16 5 4 2 3 w11 a_lat b_lat data_lock_out data_lock_out latch clk source select power/dc inputs figure 39. power connector, decoupling capacitors, dc adjust trimpot section
ad9483 C22C rev. a pcb layout the pcb is designed on a four layer (1 oz. cu) board. compo- nents and routing are on the top layer with a ground flood for additional isolation. test and ground points were judiciously placed to facilitate high speed probing. each channel has a separate 25-pin connector for its digital outputs. a common ground plane exists on the second layer. the third layer has the 3 split power planes: 1. 5 v analog for the adc and preamps, 2. 3.3 v (or 5 v) adc output supply, and 3. a separate 3.3 v supply for support logic. the fourth layer contains the C5 v plane for the preamps and additional compo- nents and routing. there is additional space for two extra com- ponents on top of the board to allow for modification. table iv. 25-pin connector pinout pin no. pin name 1 dr (data ready) 2 gnd 3a0 4a1 5a2 6a3 7a4 8a5 9a6 10 a7 11 gnd 12 nc (no connect) 13 nc (no connect) 14 drb (data ready bar) 15 gnd 16 b0 17 b1 18 b2 19 b3 20 b4 21 b5 22 b6 23 b7 24 gnd 25 nc (no connect)
ad9483 C23C rev. a figure 40. layer 1. routing and top layer ground figure 41. layer 2 ground plane
ad9483 C24C rev. a figure 42. layer 3 split power planes figure 43. layer 4 routing and negative 5 v
ad9483 C25C rev. a evaluation board parts list # qty refdes device package part number value supplier 1 54 c1-17, c19-50, capacitor 0805 c0805c104k5rac7025 0.1 m f kemit c57, c60-62, c65 2 8 c18, c51-56, c63 capacitor tajd t491c106k016as 10 m f kemit 3 16 gnd1-10, pr1, part of pcb omit pr2, pr3, pr4, pr5, pr6 4 7 j1-4, j8-10 connector smb b51-351-000-220 itt cannon 5 3 j5-7 connector bnc 227699-2 amp 6 3 p1-3 connector d 25 pins 745783-2 amp 7 9 r1-3, r14-18, r24 resistor 1206 crcw120675r0ft 75 w dale 8 9 r4-6, r11-13, resistor 1206 crcw12061001ft 1k dale r19-20, r23 9 4 r7-8, r76-77 resistor 1206 crcw12063010ft 301 w dale 10 4 r9-10, r74-75 resistor 1206 crcw120649r9ft 49.9 w dale 11 3 r21-22, r73 resistor 1206 crcw12062001ft 2k dale 12 50 r25-72, r101-102 resistor 1206 crcw12061000ft 100 w dale 13 2 r78-79 resistor 1206 crcw1206000zt 0 w dale 14 6 r80-85 resistor 1206 crcw12061500ft 150 w dale 15 3 r86, r89-90 resistor 1206 crcw12063600ft 360 w dale 16 3 r87-88, r91 resistor 1206 crcw12062740ft 274 w dale 17 3 r92, r95-96 resistor 1206 crcw12061301ft 1.3k dale 18 3 r93-94, r97 resistor 1206 crcw12061501ft 1.5k dale 19 3 r98-100 trimmer vres 3296w001501 500 w bournes 20 2 r103-105 resistor 1206 crcw12062000f 200 w dale 21 4 st1-4 part of pcb strip10 not installed 22 4 st5-8 part of pcb strip5 not installed 23 1 tb1 power connector tb8a 95f6002 wieland (2 piece) 50f3583 24 3 tp1-3 part of pcb tstpt not installed 25 1 u1 mc74lcx86d so14nb mc74lcx86d motorola 26 3 u2-4 ad9760ar so28wb ad9760ar adi 27 1 u5 AD9483KS-140/100 mq fp-100 AD9483KS-140/100 adi 28 6 u6-11 mc74lcx574dw so20wb mc74lcx574dw motorola 29 4 u12, u14-16 ad8055an so8nb ad8055an adi 30 2 u13, u17 dip20 dip20 not installed 31 6 w1-3, w8-10 2 pin jumper jmp-2p see note 32 11 w4-7, w12-18 3 pin jumper jmp-3p see note 33 1 w11 6 pin jumper jmp_6 see note 34 5 feet sj-5518 3m notes all resistors are surface mount (size 1206) and have a 1% tolerance. jumpers are samtec parts tsw-110-08-g-d and tsw-110-08-g-s. jumpers w1, w2, w3, w9, w8, w10 are omitted.
ad9483 C26C rev. a outline dimensions dimensions shown in inches and (mm). 100-lead plastic quad flatpack (s-100b) 81 100 1 50 80 31 30 51 top view (pins down) pin 1 0.685 (17.4) 0.669 (17.0) 0.555 (14.10) 0.547 (13.90) 0.015 (0.35) 0.009 (0.25) 0.921 (23.4) 0.906 (23.0) 0.742 (18.85) typ 0.791 (20.10) 0.783 (19.90) 0.029 (0.73) 0.023 (0.57) 0.486 (12.35) typ note: the ad9483ks package uses a copper insert to help dissipate heat and ensure reliable operation over the full 0 8 c to +85 8 c temperature range. this copper insert is exposed on the underside of the device. it is recommended that during the design of the pc board no throughholes or signal traces be placed under the ad9483 that could come in contact with the copper insert. commonly accepted board layout practices for high speed converters specify that only ground planes shall be located under these devices to minimize noise or distortion of video signals. 81 80 100 1 50 31 30 51 bottom view (pins up) 0.362 (9.2) 0.551 (14.0) 0.787 (20.0) 0.433 (11.0) pin 1 conductive heat sink on bottom of package seating plane 0.134 (3.40) max 0.041 (1.03) 0.031 (0.78) 0.004 (0.10) max 0.010 (0.25) min 0.110 (2.80) 0.102 (2.60) c3268aC1C12/98 printed in u.s.a.

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